⚠ Novel chemotype — no close known analogue (best Tanimoto < 0.3). Unexplored chemical space relative to ChEMBL.
Similar compounds — the chemically nearest patent molecules
Nearest neighbours by Morgan-fingerprint cosine across the patent-compound collection, with each neighbour's top predicted target and the predicted targets it shares with this molecule.
| Compound | similarity | top predicted | shared targets | |
|---|---|---|---|---|
| SCHEMBL28555395 | 1.00 | — | — | |
| SCHEMBL2159576 | 1.00 | — | — | |
| SCHEMBL31722843 | 0.87 | — | — | |
| SCHEMBL11573024 | 0.87 | — | — | |
| Water SCHEMBL27728677 | 0.87 | — | — | |
| SCHEMBL29038502 | 0.87 | — | — | |
| SCHEMBL25366216 | 0.82 | — | — | |
| SCHEMBL417334 | 0.82 | — | — | |
| SCHEMBL29371232 | 0.82 | — | — | |
| SCHEMBL150461 | 0.82 | — | — |
Similarity is cosine over the 2,048-bit Morgan fingerprint (≈ Tanimoto). Identical fingerprints score 1.00.
Patent provenance — the patents this molecule appears in, and who filed them
Claimed or disclosed in 55 patents — showing the first 20. claimed = in the patent's claims; disclosed = body only.
| Patent | Title | Assignee | Published | Priority | Filing | Country | Status |
|---|---|---|---|---|---|---|---|
| CN-117125991-A | Method for integrally preparing boride superhigh temperature ceramic coating through mixing | 大连理工大学 | 2023-11-28 | — | — | CN | claimed |
| US-8334183-B2 | Semiconductor device containing a buried threshold voltage adjustment layer and method of forming | TOKYO ELECTRON LIMITED (JP) | 2012-12-18 | — | — | US | claimed |
| US-8313994-B2 | Method for forming a high-K gate stack with reduced effective oxide thickness | TOKYO ELECTRON LIMITED (JP) | 2012-11-20 | — | — | US | claimed |
| US-20100261342-A1 | SEMICONDUCTOR DEVICE CONTAINING A BURIED THRESHOLD VOLTAGE ADJUSTMENT LAYER AND METHOD OF FORMING | TOKYO ELECTRON LIMITED (JP) | 2010-10-14 | — | — | US | claimed |
| US-20100248464-A1 | METHOD FOR FORMING A HIGH-k GATE STACK WITH REDUCED EFFECTIVE OXIDE THICKNESS | TOKYO ELECTRON LIMITED (JP) | 2010-09-30 | — | — | US | claimed |
| WO-2010111453-A1 | METHOD FOR FORMING A HIGH-K GATE STACK WITH REDUCED EFFECTIVE OXIDE THICKNESS | TOKYO ELECTRON LIMITED (JP) | 2010-09-30 | — | — | WO | claimed |
| US-7652341-B2 | Semiconductor apparatus having a semicondutor element with a high dielectric constant film | KABUSHIKI KAISHA TOSHIBA (JP) | 2010-01-26 | — | — | US | claimed |
| US-20090085175-A1 | SEMICONDUCTOR DEVICE CONTAINING A BURIED THRESHOLD VOLTAGE ADJUSTMENT LAYER AND METHOD OF FORMING | TOKYO ELECTRON LIMITED (JP) | 2009-04-02 | — | — | US | claimed |
| US-20080054378-A1 | Semiconductor apparatus and method of manufacturing the semiconductor apparatus | KABUSHIKI KAISHA TOSHIBA | 2008-03-06 | — | — | US | claimed |
| US-7265427-B2 | Semiconductor apparatus and method of manufacturing the semiconductor apparatus | KABUSHIKI KAISHA TOSHIBA (JP) | 2007-09-04 | — | — | US | claimed |
| CN-118930300-B | Heat-dredging and anti-scouring ceramic matrix composite material and preparation method thereof | 航天特种材料及工艺技术研究所 | 2025-11-25 | — | — | CN | disclosed |
| CN-117125991-B | Method for integrally preparing boride superhigh temperature ceramic coating through mixing | 大连理工大学 | 2025-11-21 | — | — | CN | disclosed |
| CN-118930300-A | Heat-dredging and anti-scouring ceramic matrix composite material and preparation method thereof | 航天特种材料及工艺技术研究所 | 2024-11-12 | — | — | CN | disclosed |
| CN-118016667-A | Semiconductor device having NMOS transistor and PMOS transistor | 爱思开海力士有限公司 | 2024-05-10 | — | — | CN | disclosed |
| US-20240153825-A1 | SEMICONDUCTOR DEVICE HAVING AN NMOS TRANSISTOR AND A PMOS TRANSISTOR | SK Hynix Inc. (KR) | 2024-05-09 | — | — | US | disclosed |
| US-20100248464-A1 | METHOD FOR FORMING A HIGH-k GATE STACK WITH REDUCED EFFECTIVE OXIDE THICKNESS | TOKYO ELECTRON LIMITED (JP) | 2010-09-30 | — | — | US | disclosed |
| US-7772073-B2 | Semiconductor device containing a buried threshold voltage adjustment layer and method of forming | TOKYO ELECTRON LIMITED (JP) | 2010-08-10 | — | — | US | disclosed |
| WO-2010027715-A1 | METHOD FOR FORMING ALUMINUM-DOPED METAL CARBONITRIDE GATE ELECTRODES | TOKYO ELECTRON LIMITED (JP) | 2010-03-11 | — | — | WO | disclosed |
| US-20100048009-A1 | METHOD OF FORMING ALUMINUM-DOPED METAL CARBONITRIDE GATE ELECTRODES | TOKYO ELECTRON LIMITED (JP) | 2010-02-25 | — | — | US | disclosed |
| US-20090085175-A1 | SEMICONDUCTOR DEVICE CONTAINING A BURIED THRESHOLD VOLTAGE ADJUSTMENT LAYER AND METHOD OF FORMING | TOKYO ELECTRON LIMITED (JP) | 2009-04-02 | — | — | US | disclosed |