⚠ Novel chemotype — no close known analogue (best Tanimoto < 0.3). Unexplored chemical space relative to ChEMBL.
Similar compounds — the chemically nearest patent molecules
Nearest neighbours by Morgan-fingerprint cosine across the patent-compound collection, with each neighbour's top predicted target and the predicted targets it shares with this molecule.
| Compound | similarity | top predicted | shared targets | |
|---|---|---|---|---|
| SCHEMBL1262491 | 0.82 | — | — | |
| SCHEMBL522700 | 0.82 | — | — | |
| SCHEMBL6004088 | 0.67 | — | — | |
| SCHEMBL995029 | 0.67 | — | — | |
| SCHEMBL3793011 | 0.67 | — | — | |
| SCHEMBL4326574 | 0.67 | — | — | |
| SCHEMBL8168121 | 0.67 | — | — | |
| SCHEMBL17766196 | 0.67 | — | — | |
| SCHEMBL3793433 | 0.67 | — | — | |
| SCHEMBL7086986 | 0.67 | — | — |
Similarity is cosine over the 2,048-bit Morgan fingerprint (≈ Tanimoto). Identical fingerprints score 1.00.
Patent provenance — the patents this molecule appears in, and who filed them
Claimed or disclosed in 1877 patents — showing the first 20. claimed = in the patent's claims; disclosed = body only.
| Patent | Title | Assignee | Published | Priority | Filing | Country | Status |
|---|---|---|---|---|---|---|---|
| US-20240243085-A1 | CONDUCTIVE BARRIER DIRECT HYBRID BONDING | ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC (US) | 2024-07-18 | — | — | US | claimed |
| US-11824080-B2 | Thin-film resistor (TFR) with displacement-plated TFR heads | MICROCHIP TECHNOLOGY INCORPORATED (US) | 2023-11-21 | — | — | US | claimed |
| CN-113223998-B | Method for manufacturing semiconductor element with inter-metal dielectric pattern | 联芯集成电路制造(厦门)有限公司 | 2022-10-04 | — | — | CN | claimed |
| WO-2022108622-A1 | ELECTRONIC FUSE (E-FUSE) WITH DISPLACEMENT-PLATED E-FUSE TERMINALS | MICROCHIP TECHNOLOGY INCORPORATED (US) | 2022-05-27 | — | — | WO | claimed |
| WO-2022108621-A1 | THIN-FILM RESISTOR (TFR) WITH DISPLACEMENT-PLATED TFR HEADS | MICROCHIP TECHNOLOGY INCORPORATED (US) | 2022-05-27 | — | — | WO | claimed |
| US-20220165530-A1 | ELECTRONIC FUSE (E-FUSE) WITH DISPLACEMENT-PLATED E-FUSE TERMINALS | MICROCHIP TECHNOLOGY INCORPORATED (US) | 2022-05-26 | — | — | US | claimed |
| US-20220157927-A1 | THIN-FILM RESISTOR (TFR) WITH DISPLACEMENT-PLATED TFR HEADS | MICROCHIP TECHNOLOGY INCORPORATED (US) | 2022-05-19 | — | — | US | claimed |
| US-11201116-B2 | Semiconductor device having inter-metal dielectric patterns and method for fabricating the same | United Semiconductor (Xiamen) Co., Ltd. (CN) | 2021-12-14 | — | — | US | claimed |
| CN-113430070-A | CoWP-compatible semi-aqueous cleaning solution, and preparation method and application thereof | 上海新阳半导体材料股份有限公司 | 2021-09-24 | — | — | CN | claimed |
| US-20210242129-A1 | SEMICONDUCTOR DEVICE HAVING INTER-METAL DIELECTRIC PATTERNS AND METHOD FOR FABRICATING THE SAME | United Semiconductor (Xiamen) Co., Ltd. (CN) | 2021-08-05 | — | — | US | claimed |
| US-20050161819-A1 | Method of treating microelectronic substrates | MICELL TECHNOLOGIES, INC. | 2005-07-28 | — | — | US | claimed |
| WO-2005034200-A2 | ADJUSTABLE SELF-ALIGNED AIR GAP DIELECTRIC FOR LOW CAPACITANCE WIRING | INTERNATIONAL BUSINESS MACHINES CORPORATION (US) | 2005-04-14 | — | — | WO | claimed |
| US-20050067673-A1 | ADJUSTABLE SELF-ALIGNED AIR GAP DIELECTRIC FOR LOW CAPACITANCE WIRING | INTERNATIONAL BUSINESS MACHINES CORPORATION (US) | 2005-03-31 | — | — | US | claimed |
| US-6638849-B2 | Method for manufacturing semiconductor devices having copper interconnect and low-K dielectric layer | WINBOND ELECTRONICS CORP. (TW) | 2003-10-28 | — | — | US | claimed |
| US-6528409-B1 | Interconnect structure formed in porous dielectric material with minimized degradation and electromigration | ADVANCED MICRO DEVICES, INC. | 2003-03-04 | — | — | US | claimed |
| US-20020192937-A1 | Method for manufacturing semiconductor devices having copper interconnect and low-K dielectric layer | WINBOND ELECTRONICS CORP. (TW) | 2002-12-19 | — | — | US | claimed |
| US-6100184-A | Method of making a dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer | SEMATECH, INC. (US) | 2000-08-08 | — | — | US | claimed |
| US-6083842-A | Fabrication of a via plug having high aspect ratio with a diffusion barrier layer effectively surrounding the via plug | ADVANCED MICRO DEVICES INC. (US) | 2000-07-04 | — | — | US | claimed |
| US-6037664-A | Dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer | AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. (SG) | 2000-03-14 | — | — | US | claimed |
| US-6015747-A | Method of metal/polysilicon gate formation in a field effect transistor | ADVANCED MICRO DEVICE (US) | 2000-01-18 | — | — | US | claimed |