⚠ Novel chemotype — no close known analogue (best Tanimoto < 0.3). Unexplored chemical space relative to ChEMBL.
Similar compounds — the chemically nearest patent molecules
Nearest neighbours by Morgan-fingerprint cosine across the patent-compound collection, with each neighbour's top predicted target and the predicted targets it shares with this molecule.
| Compound | similarity | top predicted | shared targets | |
|---|---|---|---|---|
| SCHEMBL2106157 | 0.94 | — | — | |
| SCHEMBL407670 | 0.94 | — | — | |
| SCHEMBL42699 | 0.94 | — | — | |
| SCHEMBL1190672 | 0.88 | — | — | |
| SCHEMBL4344882 | 0.88 | — | — | |
| SCHEMBL7872406 | 0.88 | — | — | |
| SCHEMBL356290 | 0.88 | — | — | |
| SCHEMBL4018138 | 0.88 | — | — | |
| SCHEMBL15105357 | 0.88 | — | — | |
| SCHEMBL644385 | 0.88 | — | — |
Similarity is cosine over the 2,048-bit Morgan fingerprint (≈ Tanimoto). Identical fingerprints score 1.00.
Patent provenance — the patents this molecule appears in, and who filed them
Claimed or disclosed in 598 patents — showing the first 20. claimed = in the patent's claims; disclosed = body only.
| Patent | Title | Assignee | Published | Priority | Filing | Country | Status |
|---|---|---|---|---|---|---|---|
| CN-118338679-A | Semiconductor device and electronic system having memory structure and related methods | 美光科技公司 | 2024-07-12 | — | — | CN | claimed |
| US-12034039-B2 | Three electrode capacitor structure using spaced conductive pillars | GLOBALFOUNDRIES SINGAPORE PTE. LTD. (SG) | 2024-07-09 | — | — | US | claimed |
| US-20240153998-A1 | SELECTIVE LOW TEMPERATURE EPITAXIAL DEPOSITION PROCESS | APPLIED MATERIALS, INC. | 2024-05-09 | — | — | US | claimed |
| US-20230415377-A1 | APPARATUS FOR PREPARATION OF SINTERED CERAMIC BODY OF LARGE DIMENSION | HERAEUS COVANTICS NORTH AMERICA LLC | 2023-12-28 | — | — | US | claimed |
| EP-4221950-A2 | SINTERED CERAMIC BODY OF LARGE DIMENSION AND METHOD OF MAKING | Heraeus Conamic North America LLC (US) | 2023-08-09 | — | — | EP | claimed |
| EP-4221949-A1 | APPARATUS FOR PREPARATION OF SINTERED CERAMIC BODY OF LARGE DIMENSION | Heraeus Conamic North America LLC (US) | 2023-08-09 | — | — | EP | claimed |
| CN-111415934-B | PMOS and NMOS integrated structure and manufacturing method thereof | 上海华力集成电路制造有限公司 | 2023-06-09 | — | — | CN | claimed |
| US-20230141031-A1 | SEMICONDUCTOR DEVICE WITH MIM CAPACITOR AND METHOD FOR MANUFACTURING SAME | HANGZHOU FULLSEMI SEMICONDUCTOR CO., LTD. (CN) | 2023-05-11 | — | — | US | claimed |
| US-20230123402-A1 | THREE ELECTRODE CAPACITOR STRUCTURE USING SPACED CONDUCTIVE PILLARS | GLOBALFOUNDRIES SINGAPORE PTE. LTD. (SG) | 2023-04-20 | — | — | US | claimed |
| CN-115692199-A | Method for improving etching uniformity | 上海华力集成电路制造有限公司 | 2023-02-03 | — | — | CN | claimed |
| US-20090004870-A1 | METHODS FOR HIGH TEMPERATURE ETCHING A HIGH-K MATERIAL GATE STRUCTURE | APPLIED MATERIALS, INC. | 2009-01-01 | — | — | US | claimed |
| EP-2009681-A2 | Methods for high temperature etching a high-k material gate structure | Applied Materials, Inc. (US) | 2008-12-31 | — | — | EP | claimed |
| WO-2008039845-A2 | FLUORINE PLASMA TREATMENT OF HIGH-K GATE STACK FOR DEFECT PASSIVATION | APPLIED MATERIALS, INC. (US) | 2008-04-03 | — | — | WO | claimed |
| US-20080076268-A1 | FLUORINE PLASMA TREATMENT OF HIGH-K GATE STACK FOR DEFECT PASSIVATION | APPLIED MATERIALS, INC. | 2008-03-27 | — | — | US | claimed |
| WO-2007121007-A2 | METHOD AND APPARATUS FOR FABRICATING A HIGH DIELECTRIC CONSTANT TRANSISTOR GATE USING A LOW ENERGY PLASMA SYSTEM | APPLIED MATERIALS, INC. (US) | 2007-10-25 | — | — | WO | claimed |
| WO-2007106660-A2 | METHOD AND APPARATUS FOR FABRICATING A HIGH DIELECTRIC CONSTANT TRANSISTOR GATE USING A LOW ENERGY PLASMA SYSTEM | APPLIED MATERIALS, INC. (US) | 2007-09-20 | — | — | WO | claimed |
| US-20070218623-A1 | METHOD OF FABRICATING A HIGH DIELECTRIC CONSTANT TRANSISTOR GATE USING A LOW ENERGY PLASMA APPARATUS | APPLIED MATERIALS, INC. | 2007-09-20 | — | — | US | claimed |
| US-20070212895-A1 | METHOD AND APPARATUS FOR FABRICATING A HIGH DIELECTRIC CONSTANT TRANSISTOR GATE USING A LOW ENERGY PLASMA SYSTEM | APPLIED MATERIALS, INC. | 2007-09-13 | — | — | US | claimed |
| US-20070212896-A1 | METHOD AND APPARATUS FOR FABRICATING A HIGH DIELECTRIC CONSTANT TRANSISTOR GATE USING A LOW ENERGY PLASMA SYSTEM | APPLIED MATERIALS, INC. | 2007-09-13 | — | — | US | claimed |
| US-6815285-B2 | Methods of forming dual gate semiconductor devices having a metal nitride layer | SAMSUNG ELECTRONICS CO., LTD. (KR) | 2004-11-09 | — | — | US | claimed |